I have experienced in working as a Hardware engineer through the full flow of Frontend design from IP development to LSI integration phases. My main roles are
- Functional design (2 years) for IP development which involved in discussing the scope of specification with customer, creating specification document, scheduling, designing within the required gatesize and timing constraint.
- Functional verification (2 years and more) for both IP and LSI in which I have to define the verification strategy, investigate the IP specifications, make the environment specification, build and/or modify the environment to support new functions, create check items and test patterns, and verify the assigned modules.
I have worked on 3 projects such as USB, Unipro 1.6/UFS 2.1, and Unipro 1.8/ UFS 3.0. including:
- Creating a checklist for checking features of test items.
- Investigating specs.
- Creating a test plan for check items
- Supporting in building the UVM environment for functional verification.
- Creating the test pattern to verify the test items by using system Verilog.
- Conducting RTL functional verification (both random and directed).
- Debugging
- Conducting functional coverage
- Keeping contact with IP designers and Product team members through Redmine.
- Running test cases by using Synopsys and Cadence tools.
- Creating a Python script to collect the test result during the regression phase
I also have experiences in:
- Training and supporting new engineers, providing training courses and sharing knowledge.
- Host the meeting to discuss and report with customers.
Achievement:
- Conducted functional verifications for 100 items/weeks
- Optimized Python script to getting a faster result.